This application relates generally to the testing of high speed DC and AC coupled interconnect circuits located between integrated circuits by extending the instruction set and architecture of the IEEE 1149.1 TAP and Boundary Scan Standard (JTAG).
The bandwidth of digital signal communication between integrated circuits on boards is increasing. New higher speed digital interconnect circuit technologies are being developed to support this need. The traditional JTAG (i.e. IEEE 1149.1 standard) boundary scan architecture has limitations that hinder it from being able to test these higher speed digital interconnect circuits.
Testing of high speed DC and AC coupled interconnect circuit between integrated circuits by JTAG is restricted due to limitations in the way the JTAG architecture performs interconnect circuit testing. Growing use of these high speed interconnect circuit will require extensions to JTAG in order to achieve reliable testing of these interconnect circuits.
An AC-Extest Working Group has done some work in addressing the testing of high speed DC and AC coupled interconnect circuits or networks. Reports of their work can be obtained over the Internet at http://www.acextest.org/.
An article by Lofstrom, Keith, “Early Capture for Boundary Scan Timing Measurements,” International Test Conference, Oct. 20-25, 1996, paper 15.3, pp. 417-422, discloses measuring analog waveforms and delays by an extension of the IEEE 1149.X standards. The extension captures samples data on a falling edge of TMS during the Update-DR state.